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Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement |
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| Authors: | M Blyzniuk I Kazymyra W Kuzmicz W A Pleskacz J Raik R Ubar |
| Affiliation: | a CAD Department and Radio-Engineering Department, Lviv Polytechnic National University, 12 Bandera St, 79013 Lviv, Ukraine;b Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, 75 Koszykowa St, 00-662 Warsaw, Poland;c Computer Engineering Department, Tallinn Technical University, 5 Ehitajate Tee, EE0026 Tallinn, Estonia |
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