一种新型的单相数字锁相环

本文提出了一种新型的高精度数字锁相环（DPLL）技术,以一个改进的鉴相器（PD）环节代替常用的二阶通用积分器构成的PD环节,为了抑制该方法在同步信号频率上引入的二次谐波干扰,本文分析了引入谐波的原因,提出针对同步信号频率二次谐波的带阻滤波器,并研究了基于FPGA的数字锁相环实现方法。该方法锁相精度高,速度快,结构简单,计算量较小。仿真和实验结果表明该方法是有效可行的。

A new single-phase digital phase-lock-loop

This paper present a new high precision digital phase-lock-loop（DPLL）. The proposed structure uses an improved phase detector（PD） to instead a PD composed by second-order generalized integrator. In order to suppress the second-order harmonic component of the tracking signal, how harmonic is drawn in is analyzed, a band-stop-filter is used to filter secondorder harmonic. This paper discusses the realization of DPLL based on FPGA. The DPLL realized by FPGA have high precision, high speed, simple structure and low computation burden. Simulation and experimental results validate its feasibility.