A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time andmemory-cell area efficiency of 33% |
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| Authors: | Yokoyama Y Itoh N Hasegawa M Katayama M Akasaki H Kaneda M Ueda T Tanaka Y Yamasaki E Todokoro M Toriyama K Miki H Yagyu M Takashima K Kobayashi T Miyaoka S Tamba N |
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| Affiliation: | Device Dev. Center, Hitachi Ltd., Tokyo; |
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| Abstract: | A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the high-speed circuit design, a multiword redundancy scheme and Y-select merged sense scheme are developed to achieve the performance goal. In the low-voltage design, a dual-complement charge-pump scheme and a decoupling capacitor utilizing a tantalum-oxide capacitor are developed to retain high performance at low supply voltage |
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