一种基于保角变换的环形栅晶体管用作ESD防护器件的建模方法

This paper proposes a novel technique for modeling the electrostatic discharge （ESD） characteristic of the enclosed-gate layout transistors （ELTs）. The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELF is decomposed into edge and comer transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM （Berkeley Short- channel IGFET Model）. Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification.

Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method

This paper proposes a novel technique for modeling the electrostatic discharge (ESD) characteristic of the enclosed-gate layout transistors (ELTs). The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELT is decomposed into edge and corner transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM (Berkeley Shortchannel IGFET Model). Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification.