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A CMOS compatible process for monolithic integration of high-aspect-ratio bulk silicon microstructures |
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| Authors: | Liang Qian ZhenChuan Yang GuiZhen Yan |
| Affiliation: | 1. MOE Key Laboratory of Instrumentation Science & Dynamic Measurement, North University of China, Taiyuan, 030051, China 3. School of Information and Electronics, Beijing Institute of Technology, Beijing, 100081, China 2. Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China 4. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Institute of Microelectronics, Peking University, Beijing, 100871, China |
| Abstract: | In this work, nanopillar-forest based surface-enhanced Raman scattering substrates were fabricated using a novel approach. The key technique of the approach is taking advantage of convexes on Poly-Si surfaces as support structures in sidewall technology. The tip-diameters of the fabricated nanopillars are from 5 to 10 nm, heights are of several microns, and density of the nanopillar-based forests is around 20/μm2. In these nanopillar forests, there are plenty of nanoscale gaps. When covered with a thin layer of noble metal, the nanopillar forests exhibit a high SERS-active capability. Primary measurement results demonstrate that the nanopillar-forest based SERS substrates have an enhancement factor of an order of 4.62 × 106. It is expected that such SERS substrates may have applications in biological monitoring and chemical detection. |
| Keywords: | monolithic integration trench isolation CMOS compatibility high-aspect-ratio bulk micromachining |
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