FPGA-based fast computation of gray-level morphological granulometries

Morphological granulometries constitute one of the most useful and versatile image analysis techniques applied to a wide range of tasks, from size distribution of objects, to feature extraction and to texture characterization in industrial and research applications where high-performance instrumentation and online signal processing are required. Since granulometries are based on sequences of openings with structuring elements (SEs) of increasing size, they are computational demanding on non-specialized hardware. In this paper, a pipelined hardware architecture for fast computation of gray-level morphological granulometries is presented, centered around two systolic-like processing arrays able to process with flat SEs of different shapes and sizes. To validate the proposed scheme, the architecture was modeled, simulated and implemented into a field programmable gate array. Implementation results show that the architecture is able to compute particle size distribution on 512 × 512 sized images with flat non-rectangular SEs of up to 51 × 51, in around 60 ms at a clock frequency of 260 MHz. It is shown that a speed up over two orders of magnitude is obtained compared to a naive software implementation. The architecture performance compares favorably to similar hardware architectural schemes and to optimized high-performance graphical processing units-based implementations.