基于中和电容的60 GHz CMOS功率放大器设计

功率放大器（Power Amplifier, PA）是射频前端重要的模块，本文基于SMIC 55 nm RF CMOS 工艺，设计了一款60 GHz 两级差分功率放大器。针对毫米波频段下，硅基CMOS晶体管栅漏电容（Cgd）严重影响放大器的增益和稳定性的问题，采用交叉耦合电容中和技术抵消Cgd影响。通过优化级间匹配网络和有源器件参数，提高了功率放大器的输出功率，增益和效率。后仿结果显示，在1.2V的供电电压下，工作在60 GHz的功率放大器饱和输出功率为11.3 dBm，功率增益为16.2 dB，功率附加效率为17.0%，功耗为62 mW。芯片面积380×570 um2 。

A CMOS 60 GHz Power Amplifier Utilizing Capacitance Neutralization

Power Amplifier (PA) is an important unit in the RF front-ends. A 60 GHz power amplifier is proposed based on SMIC 55nm RF CMOS process. Cross-coupled capacitors are utilized to neutralize the gate-drain parasitic capacitance which degrades the gain and stability performance seriously at mm-wave frequency. High output power, gain, and efficiency are achieved by optimizing the inter-stage matching networks and the active devices. The simulation results show that the PA achieves an output power of 11.3 dBm, power gain of 16.2 dB, power add efficiency (PAE) of 17.0%, and has 55.2 mW power dissipation. The chip area is 380×570 um2.