一种用于时钟数据恢复的宽带锁相环设计

锁相环广泛应用于电信、光收发器、数据存储局域网以及无线产品中，本文提出了一种新颖的应用于时钟数据恢复的锁相环设计，包括鉴频鉴相器、电荷泵、环路滤波器、换挡电路、压控振荡器以及环路状态检测电路的设计，该结构能够很好的应用于输入数据流变化范围极宽（20Mbps-2.5Gbps）的时钟数据恢复系统。设计采用了一种单供电电压的0.18um CMOS工艺，并给出Cadence环境下仿真结果。

A wide-band PLL circuit design applied in CDR

PLL has been widely used in the area of communications .A new type of PLL applied in CDR was proposed which including six parts (phase frequency detector, charge pump, loop filter, voltage controlled oscillator, gear generation, lock detector). It can meet well the demand that the input data varies from 10Mbps to 2.5Gbps in CDR . Detail simulation was given at the Cadence design environment with a 3.3V single voltage 0.18um CMOS process.