基于Verilog HDL的IIC总线IP核设计

设计片上系统时往往需要各种数据接口，为了解决片上系统间的数据传输的实际需求，设计了一种更为简捷的IIC总线接口，并利用Verilog HDL 语言进行了IIC总线IP核的设计，使得所设计的IIC总线接口具有良好的移植性，实现了不同速率模式下的数据传输，可以方便地应用到片上系统、各类集成电路数据接口等设计中。

The design of IIC bus IP core based on Verilog HDL

When doing system on a ship, various data interfaces are often needed. In order to solve the data transmission between the system on chip, the design of a more brief IIC bus interface is designed using Verilog HDL language to realize the design of IIC bus IP core, Thus, the IIC bus interface design has good portability and realizes different rates of data transmission , which also can be applied to system on chip design easily.