基于门控结构的低功耗扫描测试方案

针对芯片测试功耗过高，严重影响芯片的良率的问题，提出了门控扫描时钟方法和门控组合逻辑方法相结合的测试方案来降低芯片测试功耗。采用该测试方案，使用Synopsys公司的DFT Compiler软件，完成了一款电力网载波通信芯片的可测性设计。结果表明，该测试方案在不降低响测试覆盖率和不增加测试时间的前提下，最终将测试功耗降低了37.3%。该测试方案能够快速有效地降低芯片测试功耗，具有广泛的应用价值。

Method of Low Power Scan Test Based on Gating

The high chip testing power consumption seriously influences the chip yield. Aimed at the problem, an approach to reduce the power consumption during scan testing is proposed. The approach was realized by integrating gating scan clock method with gating logic method. The DFT design of a power line communication chip was implemented using the proposed approach with DFT Compiler in Synopsys EDA tool. The results showed that the approach reduced the power consumption during scan testing by 37.3% effectively, without affecting the test coverage and test time. The approach has wide application value.