| 射频识别接收机前端低噪声CMOS全集成频率综合器关键模块设计 |
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| 引用本文： | 陈磊,雷奥,谢传文,赖宗声.射频识别接收机前端低噪声CMOS全集成频率综合器关键模块设计[J].吉林大学学报(工学版),2009(Z1). |
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| 作者姓名： | 陈磊 雷奥 谢传文 赖宗声 |
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| 作者单位： | 华东师范大学微电子电路与系统研究所;华东师范大学纳光电集成与先进装备教育部工程研究中心; |
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| 基金项目： | 上海市科委项目(07SA04);;上海重点学科建设项目(B411) |
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| 摘 要： | 为满足射频识别接收机相位噪声性能要求,在分析了频率综合器整体噪声机制的基础上,将偶次谐波抑制电路应用于1.8 GHz压控振荡器设计并采用注入锁定高速与分频器结构,鉴频鉴相器PFD设计改善了相位死区,在整体上改善了频率综合器相位噪声。利用0.25μm 1P6M RFCMOS工艺,完成了频率综合器的完整版图设计。仿真结果表明:VCO调谐范围达到47.2%,电路整体相位噪声达到-128 dBc/Hz@1 MHz,完全满足应用要求。
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| 关 键 词： | 电子技术 射频识别 频率综合器 相位噪声 |
Key blocks design of CMOS full-integrated frequency synthesizer in RFID receiver |
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| CHEN Lei,LEI Ao,XIE Chuan-wen,LAI Zong-sheng.Key blocks design of CMOS full-integrated frequency synthesizer in RFID receiver[J].Journal of Jilin University:Eng and Technol Ed,2009(Z1). |
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| Authors: | CHEN Lei LEI Ao XIE Chuan-wen LAI Zong-sheng |
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| Affiliation: | 1.Institute of Microelectronics Circuit & System;East China Normal University;Shanghai 200062;China;2.Engineering Research Center for Nanophotonics & Advanced Instrument;Ministry of Education;China |
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| Abstract: | Based on analysis of overall phase noise mechanism in frequency synthesizer,to meet the constraints of RFID receiver,a series of new methods was proposed,involving employing even harmonics inhibition in 1.8 GHz VCO core,high-speed SCL dividers and improving PFD structure by elimination of "Dead Zone".The simulation results show that fabricated by 0.25 μm 1P6M RFCMOS process,the overall phase noise in frequency synthesizer reaches-128 dBc/Hz@1 MHz,which fully meet the EPC requirements. |
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| Keywords: | electronics RFID frequency synthesizer phase noise |
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