布线后修复时序违规的方法研究

90／65nm下后端设计中由于多模式一角落，以及布局布线工具和签收工具之间的误差性，布线后修复各种时序违规如渡越时间、负载、建立时间、保持时间、串扰等将是一项十分耗时的工作。如何快速修复各种违规，取得设计收敛是后端设计者所关注的。本文分析了各种情况，提供了一些解决方案。

Methodology research on fixing timing violations during post-route

In IC backend design under 90/65nm, due to multi- mode multi- corner as well as correlation problems between place & route tools and signoff STA tools, the fixing timing violations such as slew/load, setup/hold, crosstalk during postroute stage remains a nontrivial and tedious work. Backend designer trys to remove these violations to achieve timing closure faster. In this paper, all the problems have been analyzed, together with corresponding solutions for your reference.