深亚微米CMOS电路漏电流快速模拟器

随着工艺的发展 ,功耗成为大规模集成电路设计领域中一个关键性问题 降低电源电压是减少电路动态功耗的一种十分有效的方法 ,但为了保证系统性能 ,必须相应地降低电路器件的阈值电压 ,而这样又将导致静态功耗呈指数形式增长 ,进入深亚微米工艺后 ,漏电功耗已经能和动态功耗相抗衡 ,因此 ,漏电功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫 诸如HSPICE的精确模拟器可以准确估计漏电功耗 ,但仅仅适合于小规模电路 首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应 ,然后提出了快速模拟器的漏电模型 ,最后通过对ISCAS85& 89基准电路的实验 ,说明了在精度许可 (误差不超过 3% )的前提下 ,模拟器获得了成百倍的加速 ,同时也解决了精确模拟器的内存爆炸问题

Leakage Power Simulator of CMOS Circuit Under DSM Process

As technology evolves, power dissipation has become a critical issue of VLSI circuit design Lowering power supply voltage is an efficient method to reduce dynamic power In order to maintain performance, the threshold voltage of a device should be reduced accordingly, which results in an exponential increase of static power When entering into deep sub micron (DSM) process era, leakage power becomes comparable with dynamic power consumption Fast simulators are urgently needed just as are low leakage design technologies Precise circuit simulators (such as HSPICE) can accurately account for leakage power estimation, but are only practical for small circuits Firstly, in this paper, the stack effect of CMOS transistors and primitive logic gates is demonstrated based on which a leakage model of the simulator is put forward And then experiments on ISCAS?85&89 benchmark circuits are given to show this simulator is hundredfold accelerated compared with HSPICE with endurable accuracy (error under 3%), the memory explosion problem of accrate simulator is also solved in the same time