| 高效率集成电路测试芯片设计方法 |
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| 引用本文： | 胡龙跃,史 峥,刘得金,邵康鹏.高效率集成电路测试芯片设计方法[J].计算机工程与应用,2013,49(11):54-57. |
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| 作者姓名： | 胡龙跃 史 峥 刘得金 邵康鹏 |
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| 作者单位： | 浙江大学 超大规模集成电路设计研究所，杭州 310027 |
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| 摘 要： | 对生成测试芯片效率进行研究，提出了一种采用版图编辑器作图和批量参数化建模设计方法。缩短了设计周期，降低了设计难度。依据该方法，开发了一套针对工艺开发包的测试芯片，实验结果验证了其高效性。
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| 关 键 词： | 超大规模集成电路 测试芯片 开尔文结构 工艺开发包 组件描述格式 |
Highly efficient design method of test chip for VLSI |
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| HU Longyue,SHI Zheng,LIU Dejin,SHAO Kangpeng.Highly efficient design method of test chip for VLSI[J].Computer Engineering and Applications,2013,49(11):54-57. |
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| Authors: | HU Longyue SHI Zheng LIU Dejin SHAO Kangpeng |
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| Affiliation: | Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China |
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| Abstract: | To study the efficiency of generating VLSI test chip, a method which uses a layout editor for drawing and models parameters in batch is proposed. This method can not only shorten design cycle, but also reduce difficulty. A set of test chips for PDK has been implemented by the method, and the final result proves the efficiency. |
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