| 一种LDO线性稳压电路设计 |
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| 引用本文： | 程军,邬小林,周民,杨维明. 一种LDO线性稳压电路设计[J]. 现代电子技术, 2010, 33(6): 16-18,28 |
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| 作者姓名： | 程军 邬小林 周民 杨维明 |
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| 作者单位： | 1. 武汉职业技术学院,湖北,武汉,430074
2. 湖北大学,物理学与电子技术学院,湖北,武汉,430062 |
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| 基金项目： | 湖北省教育厅重点科研资助项目 |
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| 摘 要： | 采用CSMC0．5μm40V工艺和Spectrum仿真平台，设计一款应用于电压保护芯片的LDO（Low Dropout）低压差线性稳压电路。该电路选择PMOS结构的调整管，不需要增加额外的电荷泵电路来驱动；采用带隙基准电压源结构，在1kHz频率下，电源电压抑制比（PSRR）为-67．32dB，在1MHz频率下为-33．71dB；在误差放大器设计中引入频率补偿，改善了稳压器的线性调整率性能。仿真结果表明，常温下当输入电压从1．6V变化到6．6V时，输出电压稳定在1．258V左右，温度系数为31．38ppm，在100kΩ负载下显示出良好的稳压性能。
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| 关 键 词： | 低压差 线性稳压电路 高电源抑制比 电荷泵电路 |
Design of LDO Linear Voltage Stabilizer |
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| CHENG Jun,WU Xiaolin,ZHOU Min,YANG Weiming. Design of LDO Linear Voltage Stabilizer[J]. Modern Electronic Technique, 2010, 33(6): 16-18,28 |
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| Authors: | CHENG Jun WU Xiaolin ZHOU Min YANG Weiming |
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| Affiliation: | CHENG Jun1,WU Xiaolin2,ZHOU Min2,YANG Weiming2(1.Wuhan Institute of Technology,Wuhan,430074,China,2.The School of Physics & Electronic Technology,Hubei University,430062,China) |
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| Abstract: | Low dropout linear voltage stabilizer for voltage protection is presented. The circuit is designed in CSMC 0.5 μm 40 V technology and simulated by spectrum tool. Since PMOS adjustment transistor is selected, the additional charge pump driving circuit is not needed. The band - gap voltage reference structure is employed. The PSRR is - 67.32 dB at 1 kHz and -33.71 dB at 1 MHz. The frequency compensation network is used in the error amplifier design to improve the performance of linear adjustment ratio. The simulation results that the reference voltage is about 1. 258 V while the input voltage varies from 1.6 V to 6.6 V at the room temperature,the temperature coefficient is 31.38 ppm. The circuit shows good voltage stabilizer ability under 100 kΩ load. |
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| Keywords: | low dropout linear voltage stabilizer high PSRR charge pump circuit |
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