减少SOC测试时间的测试结构配置与规划

以减少系统芯片(SOC)测试时间为目标,研究了基于内嵌芯核分簇的并行测试结构配置与规划问题。以求解多处理器规划问题为模型,分析了并行测试层次型SOC多芯核的规划,重点研究了最小化测试时间目标下多芯核最优分簇问题。以ITC2002SOCBenchmark为实验对象,示例了芯核分簇的规划结果。该方法可用于SOC并行测试流程控制及SOC的可测性设计。

Test Structure Configuration and Schedule to Reduce Test Time of System-on-a-chip

Test structure configuration and schedule problem during parallel test is studied based on clustering of embedded cores while aiming at reduction of test application time of system-on-a-chip(SOC).Based on the solution of multiple-processors-schedule, schedule problem about parallel test of multiple cores in hierarchical SOC is analyzed also. Emphasis is placed on optimal clustering of cores in SOC under the objective of minimal test time. ITC2002 Benchmark SOC exemplified schedule results of cores clustering. the approach presented can be used to control parallel test flow and design for testability of SOC.