Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators

This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling /spl Delta//spl Sigma/ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the /spl Delta//spl Sigma/ modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the /spl Delta//spl Sigma/ modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order /spl Delta//spl Sigma/ modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1-pF capacitors is designed in a 0.25-/spl mu/m standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.