低相噪频率合成器中环路滤波器仿真研究

为了改善短波跳频电台中频率合成器的相位噪声特性,分析了DDS激励PLL式频率合成器中锁相环单元工作过程,基于ADI公司的PLL芯片ADF4001,就相位噪声问题对环路滤波器进行了设计.从带宽和相位余量出发,通过一种参数的近似算法,重新计算设定滤波器各种参数值,有效降低了滤波器相位噪声.最后用ADIsimPLL仿真软件对锁相环进行了仿真.结果表明：在70MHz输出时,经计算调整后的系统噪声性能比调整前优化可达0.79%,滤波器噪声性能的优化可达4%.有效改善了频率合成器的相位噪声特性.

Simulation of Loop Filter on Low Phase Noise Frequency Synthesizers

To improve the phase noise performance of the frequency synthesizers of frequency hopping radio in SW band,the operating process of PLL unit in the frequency synthesizer with DDS-driven PLL was analyzed,and the loop filter was designed by using ADI corporations＇ PLL chip ADF4001,aimed at the phase noise.In terms of the bandwidth and the phase margin,the various parameters of the filter were re-calculated and set by using the method of one kind of parameters＇ approximation,reducing the filters’phase noise effectively.Finally,by simulation over ADIsimPLL software on PLL it is shown that the adjusted system noise performance is optimized by 0.79% in the 70 MHz output.The optimization of filters＇ noise performance is up to 4%,thus improving the phase noise performance of the frequency synthesizers efficiently.