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The MAJC architecture: a synthesis of parallelism and scalability |
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| Authors: | Tremblay M. Chan J. Chaudhry S. Conigliam A.W. Tse S.S. |
| Affiliation: | Sun Microsyst; |
| Abstract: | The MAJC architecture enhances application performance by exploiting parallelism at multiple levels-instruction, data, thread, and process. Supporting vertical multithreading, speculative multithreading, and chip multiprocessors, the scalable VLIW architecture is also capable of advanced speculation and predication and treats all data types similarly |
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