考虑噪声效应的VDSM延时测试生成方法

为了解决超深亚微米芯片的延时测试问题，首先提出了一种新的基于布尔过程论的逻辑级噪声预测方法，用波形多项式描述的同时发生的跳变数来预测噪声大小，并生成能产生最大跳变数目的输入波形；然后同基于波形敏化的长敏化通路选择法相结合，提出了一种基于布尔过程论的能产生最大噪声效应的敏化测试波形生成方法。实验表明，本文提出的方法可以应用在复杂电路的延时故障测试中，有较好的推广价值。

Generation of VDSM delay test with noise effects taken into consideration

To solve delay test problems for VDSM ehips, a novel noise prediction method based on Boolean process is proposed for running delay test of VDSM chips with transition numbers used to describe noise effects. With long sensitizable paths selected according to the waveform sensitization, the noisiest input waveform can be generated for long sensitizable paths. Experimental results show that the method proposed can be used for running delay test of complex circuits.