Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs |
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| Authors: | T Sansaloni A Pérez-Pascual V Torres and J Valls |
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| Affiliation: | (1) Department of Electronic Engineering, Polytechnic University of Valencia, EPSG, Carretera Nazaret-Oliva s/n, Grao de Gandía, 46730, Spain |
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| Abstract: | A scheme for reducing the hardware resources to implement on LUT-based FPGA devices the twiddle factors required in Fast Fourier
Transform (FFT) processors is presented. The proposed scheme reduces the number of embedded block RAM for large FFTs and the
number of slices for FFT lengths higher than 128 points. Results are given for Xilinx devices, but they can be generalized
for other advanced LUT-based devices like ALTERA Stratix.
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| Keywords: | Fast Fourier Transform digital circuits digital communications |
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