Double-polysilicon SiGe HBT architecture with lateral base link

We present an analysis of a modified double-polysilicon SiGe:C HBT module showing a CML ring oscillator gate delay τ_D of 2.5 ps, and f_T/f_max/BV_CEo values of 300 GHz/350 GHz/1.85 V (Fox et al., 2008) [1]. A key feature of the HBT module is a connection of the extrinsic and intrinsic base regions by lateral epitaxial overgrowth, which aims to overcome the limits of the conventional double-polysilicon architecture in simultaneously reducing R_B and C_BC. Potential benefits and barriers of the proposed device structure on the way to higher performance are reviewed with regard to the recently demonstrated performance gain of the classical double-polysilicon approach. The paper addresses technological challenges one is faced when the here presented device structure is scaled to minimum device dimensions.