| Abstract: | This paper deals with a new approach to the design of high-performance asynchronous pipelined datapaths. A novel methodology to implement the self-timed stages of a data-path is demonstrated. It is based on the use of both static and dynamic CMOS modules. The former act as overlapped execution circuits and anticipate their computation with respect to the dynamic blocks. An appropriate four-phase protocol able to orchestrate the proposed architecture and a new efficient handshake circuit are described. The above method, applied to a 32-bit addition stage, allows a performance gain to be obtained of up to about 40% and a reduction in power dissipation of about 33%, with a reasonable area overhead compared with conventional designs. |
