A theoretical study of the performance of sub-micron MOSFET devices in the presence of edge potential

In the present communication we have presented a detailed theoretical analysis of the performance of the sub-micron device in the presence of the discontinuity at the Si–SiO₂ interface. It is assumed that due to interface discontinuity a potential develops at the edges (Source/Drain) in addition to the built-in-potential. This potential, called Edge Potential, measures directly the extent of the interface roughness. The effect of this potential is more critical in the case of short channel device where drain and source are in close proximity. Our analysis shows that the discontinuity is dominant at the edges but not in the channel. Drive current as well as saturation transconductance decreases in the presence of edge potential. These results suggest that the performance of the device degrades due to the interface roughness. Effect of interface roughness near the edges can be reduced at high gate voltage but it will result more interface roughness scattering.