Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET |
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Authors: | Rajneesh Sharma Ashwani K. Rana |
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Affiliation: | 1. Department of Electronics and Communication, National Institute of Technology Hamirpur, Hamirpur, Indiarajnish1ece@gmail.com;3. Department of Electronics and Communication, National Institute of Technology Hamirpur, Hamirpur, India |
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Abstract: | In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters. |
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Keywords: | Fully Depleted Silicon-On-Insulator (FDSOI) underlap structure two-dimensional (2-D) analytical model surface potential short-channel effects |
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