Quaternary static latch circuit |
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| Authors: | K W Current |
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| Affiliation: | 1. Centre of Millimeter-Wave Semiconductor Devices and Systems (CMSDS, a joint venture of DRDO, Ministry of Defence Government of India and University of Calcutta), Centre of Advanced Study in Radio Physics and Electronics, University of Calcutta , Kolkata 700009, India mou_mita_m@yahoo.com mukherjee_mita@hotmail.com;3. IERCEM Institute of Information Technology, West Bengal University of Technology, 24 Parganas (N) 743233 , Kolkata, India;4. Centre of Millimeter-Wave Semiconductor Devices and Systems (CMSDS, a joint venture of DRDO, Ministry of Defence Government of India and University of Calcutta), Centre of Advanced Study in Radio Physics and Electronics, University of Calcutta , Kolkata 700009, India |
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| Abstract: | A new voltage-mode quaternary CMOS static latch circuit is presented. Only devices available in a standard digital CMOS fabrication technology—enhancement-mode NMOS and PMOS transistors with single threshold voltage values—are used. No depletion-mode devices or special transistor threshold voltages are required. Three reference voltages and ground are used to define the logic levels. The operation of the quaternary latch is experimentally verified. Using data for a standard 2-micron digital CMOS fabrication technology, best- and worst-case on-chip setup and hold times are estimated, using simulation, to be approximately 2.8 ns and 6.8 ns, respectively. |
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| Keywords: | InP IMPATT oscillators top-mounted diode flip-chip diode photo-illumination double-drift-region terahertz characteristics parasitic series resistance frequency chirping |
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