The limiting performance of a CMOS bistable register based on waveform considerations

The fundamental latching behaviour of a CMOS bistable register is described. The circuit response of two cross coupled NAND gates being driven by a data and a clock signal can be decomposed into four individual regions of operation. Closed form small signal solutions for each region of operation are described and favourably compared with SPICE. The third region of operation contains the closed loop regenerative mode of operation inherent to the bistable NAND gate configuration and fundamental to the latching behaviour of a register. From these results, necessary and sufficient conditions for latching data into a bistable register are developed. Finally, from these necessary and sufficient conditions, the limiting condition for latching is presented and verified by SPICE.