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Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications |
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| Authors: | S Moorthi D Meganathan D Janarthanan P Praveen Kumar J Raja Paul Perinbam |
| Affiliation: | 1. Department of Electrical and Electronics Engineering , National Institute of Technology , Tiruchirappalli-15, Tamilnadu, India srimoorthi@nitt.edu;3. Department of Electronics Engineering , MIT Campus, Anna University , Chennai, 600 044, Tamilnadu, India;4. Department of Electronics and Communication Engineering , College of Engineering, Anna University , Chennai, 600 025, Tamilnadu, India |
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