| PCI总线双向FIFO缓冲并行通信的实现 |
| |
| 引用本文： | 戴志涛. PCI总线双向FIFO缓冲并行通信的实现[J]. 微处理机, 2002, 0(3): 53-55,64 |
| |
| 作者姓名： | 戴志涛 |
| |
| 作者单位： | 北京邮电大学计算机科学与技术学院,北京,100876 |
| |
| 摘 要： | 介绍一种基于PCI总线、带有FIFO缓冲器的处理机间高速双向并行通信机制，给出了并行通信接口电路、处理机间的同步控制逻辑及其软件控制流程。
|
| 关 键 词： | PCI总线 双向FIFO缓冲 并行通信 处理机 FIFO存储器 |
Implementation of PCI Bus Parallel Communication with Bidirectional FIFO Buffers |
| |
| Dai Zhitao. Implementation of PCI Bus Parallel Communication with Bidirectional FIFO Buffers[J]. Microprocessors, 2002, 0(3): 53-55,64 |
| |
| Authors: | Dai Zhitao |
| |
| Abstract: | A PCI bus high-rate,bidirectional,interprocessor parallel communication mechanism is described.The parallel communication interface circuit,the interprocessor synchro-control logic and the software control flow are provided. |
| |
| Keywords: | PCI bus parallel communication multi-set communication FIFO memory |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
