Wafer-applied underfill: flip-chip assembly and reliability |
| |
Authors: | Johnson RW Qing Wang Fei Ding Zhenwei Hou Crane L Hao Tang Shi G Renzhe Zhao Danvir J Jing Qi |
| |
Affiliation: | Lab. for Electron., Auburn Univ., AL, USA; |
| |
Abstract: | Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is not a typical process for a surface-mount technology (SMT) factory, and demands additional capital equipment, floor space, cycle time, and headcount. An alternate approach to traditional capillary underfill is wafer-applied underfill. The underfill is applied after wafer bumping and sawing, but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly processes. Liquid-to-liquid thermal cycle shock tests (-55 to +125/spl deg/C) have been performed on test vehicles assembled with the wafer-applied underfill. First failures were at over 1000 cycles. Weibull plots of the data and failure analysis are presented. |
| |
Keywords: | |
|
|