Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure |
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Authors: | Kato I. Horie H. Oikawa K. Taguchi M. |
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Affiliation: | Fujitsu Ltd., Kawasaki; |
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Abstract: | To investigate the highly boron-doped SiO2 film, p+ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n+-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO2 interface and electrons accumulate near the polysilicon/SiO2 interface in p+-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p+ gate's stress time dependence of Isub is smaller than that of the n+ gate, and the electric field near the drain in the p+ -gate PMOSFET was found to be more severe than that of the n+ -gate device. The subthreshold slope of the p+-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n+-gated device did not significantly change. The actual change of Vth was larger than the value derived from Δgm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO2 film, which assumes the existence of trapped holes in the p+-gate PMOSFET, is proposed to explain these phenomena |
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