| H.264中DCT/IDCT/Hadamard变换多时钟方式的FPGA实现 |
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| 引用本文： | 王一皓,陈磊,于鸿洋. H.264中DCT/IDCT/Hadamard变换多时钟方式的FPGA实现[J]. 中国有线电视, 2007, 0(8): 754-757 |
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| 作者姓名： | 王一皓 陈磊 于鸿洋 |
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| 作者单位： | 电子科技大学,四川,成都,610054 |
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| 摘 要： | DCT/IDCT/Hadamard变换被广泛应用于多种视频编码标准中,而H.264/MPEG-4AVC作为新一代的视频压缩标准,它具有在相同图像质量下比其他视频压缩标准拥有更高的压缩率的特性[1],因此对于H.264/MPEG-4AVC中的DCT/IDCT/Hadamard变换的研究就有着十分重要的意义。对于H.264/MPEG-4AVC中变换算法进行分析,并且提出一种可用的高效的硬件实现电路结构,此电路结构能够并行计算4输入像素数据。
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| 关 键 词： | H.264标准 整数DCT/哈达玛 现场可编程门阵列 |
| 文章编号： | 1007-7022（2007）08-0754-04 |
| 收稿时间： | 2007-01-24 |
| 修稿时间： | 2007-01-24 |
A Multi-clock Domain FPGA Implementation of DCT/IDCT/Hadamard in H.264 |
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| WANG Yi-hao,CHEN Lei,YU Hong-yang. A Multi-clock Domain FPGA Implementation of DCT/IDCT/Hadamard in H.264[J]. China Cable Television, 2007, 0(8): 754-757 |
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| Authors: | WANG Yi-hao CHEN Lei YU Hong-yang |
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| Affiliation: | University of Electronic Science and Technology, Sichuan Chengdu 610054, China |
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| Abstract: | DCT/IDCT/Hadamard transform coding has been widely used in video coding standards. Under the same picture quality, MPEG-4AVC/H.264, as a new video coding standard, can realize a higher bit-rate reduction and improvement in coding performance[1]. It is very important to study the DCT/IDCT/Hadamard in MPEG-4AVC/H.264. In this paper, a hardware architecture for accelerate DCT/IDCT/Hadamard transformation coding is presented. This architecture can calculate 4 inputs in parallel. |
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| Keywords: | H.264 standard DCT/IDCT/Hadamard FPGA |
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