Core与总线系统的异步通信接口设计

文章基于GALS（Globally Asynchronous Locally Synchronous）设计理念，提出一个Core的异步接口设计模型：门控时钟停Core机制、握手机制、电平转脉冲逻辑等构成的异步控制信号处理模型：异步FIFO和双FIFO结构构成的异步数据处理模型。此结构允许Core和总线系统在完全异步的时钟域上工作。FPGA验证结果表明．该模型能正确地实现两者问的信号同步，并能满足具体应用的带宽需求。

An Interface Design for Asynchronous Communication Between Core and Bus System

Based on the concept GALS(Globally Asynchronous Locally Synchronous), an asynchronous interface design model for Core is introduced in this article:asynchronous control signal model is made up of Core stall policy based on Gated clock, handshake protocol, level to pulse logic and so on; asynchronous data model is made up of asynchronous FIFO and dual FIFO architecture. This model permits Core and Bus System work on two unrelated clock frequency. Proved in FPGA verification, it can not only realize signal synchronization correctly, but also satisfy bandwidth demand for application.