一种新的基于可配置处理器的异构多核线程级动态调度模型

本文针对基于可配置处理器的异构多核结构，提出一种新的线程级动态调度模型。此类异构多核系统中每个核分别针对某一应用做指令集扩展，调度器通过线程、处理器核以及指令集间的映射关系，动态调度线程至适合的处理器核，从而在没有大幅增加芯片面积的前提下，达到与每个核都具有全扩展指令集相近似的加速比，此外该模型还可以有效减少编程模型的复杂度。

A novel thread level dynamic scheduling model for heterogeneous MPcore based on configurable processor

This paper proposes a novel thread level dynamic scheduling model. Through the relationships among processor cores, instruction sets (ISA) and threads, this model is able to dynamically assign a thread to a configurable processor core with partially instruction extension in heterogeneous multi-core architecture, which can speed up the performance with less area increasing than full instruction extension SMP architecture, and simplify the programming model.