| 基于边界扫描技术的SOC数字电路可测性设计 |
| |
| 引用本文： | 周银,刘荣昌,陈圣俭,王蒙蒙. 基于边界扫描技术的SOC数字电路可测性设计[J]. 微电子学, 2011, 41(5) |
| |
| 作者姓名： | 周银 刘荣昌 陈圣俭 王蒙蒙 |
| |
| 作者单位： | 1. 装甲兵工程学院控制工程系,北京,100072
2. 中国北方车辆研究所,北京,100072 |
| |
| 基金项目： | 国家自然科学基金资助项目(60871029) |
| |
| 摘 要： | 随着SOC系统的快速发展,如何对其进行有效的测试与诊断是当前研究的热点问题。从SOC数字电路可测试性设计的角度出发,基于边界扫描技术,设计了具有边界扫描结构的IP核,并对相应的测试方法进行了研究。通过仿真及时序分析,验证了该设计方法的可行性,为SOC系统的测试提供了新的思路。
|
| 关 键 词： | SOC 数字电路 IP核 边界扫描 可测性设计 IEEE1149.1 |
Design for Testability of Digital Circuit in SOC Based on Boundary-Scan |
| |
| ZHOU Yin,LIU Rongchang,CHEN Shengjian,WANG Mengmeng. Design for Testability of Digital Circuit in SOC Based on Boundary-Scan[J]. Microelectronics, 2011, 41(5) |
| |
| Authors: | ZHOU Yin LIU Rongchang CHEN Shengjian WANG Mengmeng |
| |
| Affiliation: | ZHOU Yin1,LIU Rongchang2,CHEN Shengjian1,WANG Mengmeng1(1.Department of Control Engineering,Accademy of Armored Force Engineering,Beijing 100072,P.R.China,2.China North Vehicle Research Institute,P.R.China) |
| |
| Abstract: | With rapid development of SOC,its test and diagnosis is becoming a research subject of interest.From the viewpoint of design-for-testability of digital circuits in SOC,an IP core with boundary-scan architecture was designed and corresponding test strategies were studied.Feasibility of the design methodology was validated by simulation and experimental results,which provided a novel approach for SOC test. |
| |
| Keywords: | SOC Digital circuit IP core Boundary-scan Design for testability IEEE 1149.1 |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
