| 基于无冲突多项式交织器的高速并行Turbo解码器 |
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| 引用本文： | 陈琳,王小力.基于无冲突多项式交织器的高速并行Turbo解码器[J].微电子学,2011,41(6). |
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| 作者姓名： | 陈琳 王小力 |
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| 作者单位： | 西安交通大学电子与信息工程学院,西安,710049 |
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| 摘 要： | 提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量.
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| 关 键 词： | Turbo解码器 QPP 无冲突交织器 存储器映射 |
Implementation of High-Speed Parallel Turbo Decoder Based on High-Degree Polynomial Interleaver |
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| CHEN Lin
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WANG Xiaoli.Implementation of High-Speed Parallel Turbo Decoder Based on High-Degree Polynomial Interleaver[J].Microelectronics,2011,41(6). |
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| Authors: | CHEN Lin WANG Xiaoli |
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| Affiliation: | CHEN Lin,WANG Xiaoli(School of Electronics and Information,Xi'an Jiaotong University,Xi'an 710049,P.R.China) |
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| Abstract: | Optimized implementation of a high speed parallel turbo decoder was proposed based on contention-free high-degree polynomial interleaver.The decoder,for which MAX-Log-MAP decoding algorithm was used,focused on QPP interleaver included in long term evolution(LTE) turbo code.The design was implemented with m language on Matlab,and verified with Verilog HDL.The parallel decoder was tested on LTE simulation system based on FPGA.The decoder achieved a 6.9 bit/cycle in half iteration and a throughput of 207 Mbit/... |
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| Keywords: | Turbo decoder QPP Contention-free interleaver Memory mapping |
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