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| 7位80MS/s电流模式折叠分级式模数转换器 | |
| 引用本文： | 王百鸣,洪岳炜,陈静秋,孟晓胜,李琰.7位80MS/s电流模式折叠分级式模数转换器[J].微电子学,2011,41(5). |
| 作者姓名： | 王百鸣 洪岳炜 陈静秋 孟晓胜 李琰 |
| 作者单位： | 1. 深圳大学信息工程学院EDA技术中心,广东深圳,518060 2. 深圳大学光电子学研究所,广东深圳,518060 3. 华中科技大学光电子科学与工程学院,武汉,430074 4. 深圳市嵌入式系统设计重点实验室,广东深圳,518060 |
| 基金项目： | 国家自然科学基金资助项目(90407001;60901016) |
| 摘 要： | 提出了一种基于电流模式的折叠分级式A/D转换器(ADC),分析了电路原理和结构,阐述了如何提高ADC的性能。测试表明,电路已达到相关性能指标。转换速率为80MS/s,在3.0MHz输入信号下的信噪失真比(SINAD)为44.4dB,有效位数(ENOB)为7.1位。给出了已实现ADC电路的结构、测试波形和动态性能测试结果。 |
| 关 键 词： | A/D转换器 折叠分级 电流模式 模拟余差 |
A 7-Bit 80-MS/s Current-Mode Folded Subranging A/D Converter |
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| WANG Baiming,HONG Yuewei,CHEN Jingqiu,MENG Xiaosheng,LI Yan.A 7-Bit 80-MS/s Current-Mode Folded Subranging A/D Converter[J].Microelectronics,2011,41(5). | |
| Authors: | WANG Baiming HONG Yuewei CHEN Jingqiu MENG Xiaosheng LI Yan |
| Affiliation: | WANG Baiming1,HONG Yuewei2,CHEN Jingqiu3,MENG Xiaosheng2,LI Yan4(1.EDA Technol.Center,College of Inform.Engineer.,Shenzhen Univ.,Shenzhen,Guangdong 518060,P.R.China,2.Institute of Optoelectronics,Shenzhen University,3.Institute of Optoelectronics and Engineering,Huazhong University of Science and Technology,Wuhan 430074,4.Shenzhen City Key Laboratory of Embedded System Design,P.R.China) |
| Abstract: | A current-mode folded subranging A/D converter was presented.The operational principle and structure of the circuit were analyzed.Key issues associated with improvement of ADC performance were elaborated.Test results showed that the proposed ADC achieved a sampling rate of 80 MS/s,an SINAD of 44.4 dB and an ENOB of 7.1 bits for 3.0 MHz input signal.Architecture of the proposed ADC was described.Test waveforms were presented and dynamic parameters were discussed in detail. |
| Keywords: | A/D converter Folded subranging Current mode Residue of analogue quantity |
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