CPLD在中压变频控制器中的应用与研究

SPWM（弦脉宽调制）多电平叠加变频技术计算复杂，输出脉冲路数多，系统实时性要求高。采用单片DSP作为其控制器核心器件，不能满足控制器实时性要求；多片DSP协同工作，需要交换总线控制权而消耗核心DSP时间资源．并且也不能满足脉冲输出端口数量。DSP与CPLD两者协调工作，很好地解决了这些问题，另外该种技术方案开发周期短，生产成本低。本文正是以此为背景展开研究，详细论述CPLD功能总体设计、硬件选型设计与脉冲形成CPLD软件开发流程，并且给出了系统运行波形图。

The application and research of the CPLD in medium valtage variable-frequency controller

The computation of the technology of the SPWM multi-power level adding is very complex ,but also the number of branch of distribution of pulse are many ,at the same time ,its system controlling faces with a real-time problem. The single DSP chip as the controlling core is very difficult to meet with the controlling real-time characteristic requirements for use , the collaborative work of several DSP chips needs exchanging the control power of system bus ,so the time resources of core DSP, at mean time , the number of branch of distribution of pulse is too few to use .However DSP combined with the CPLD consistently supplies a good method to resolve these problems. On the side, the period of development is less and the cost of development is lower . This paper takes this as the background for studying , it describes in detail the process of design of CPLD function general design and hardware model selection. And the software development cycle and the waveform graph of system operation are given.