LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits

The results of a numerical and experimental study aimed at increasing the holding on-state voltage of a low-voltage triggered silicon controlled rectifier are presented. Using TCAD numerical simulations two solutions are presented that are based on emitter injection control by the modification of the emitter–drain area ratio and by the addition of internal diodes in the emitter line. Experimental data generated in a 0.18 μm CMOS technology demonstrate the effectiveness of the new low-voltage triggered silicon controlled rectifier (LVTSCR) structures and validates the simulation results. It has been demonstrated that for the LVTSCR structures with high holding voltage the electrostatic discharge efficiency is 3–5 times higher than that of a conventional grounded gate snapback NMOS and simultaneously has 50% lower RF load capacitance.