| 小面积低功耗掩膜ROM ASIC设计 |
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| 引用本文： | 崔嵬,韩月秋,陈禾,李昀. 小面积低功耗掩膜ROM ASIC设计[J]. 电子学报, 2002, 30(6): 934-936 |
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| 作者姓名： | 崔嵬 韩月秋 陈禾 李昀 |
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| 作者单位： | 北京理工大学电子工程系,北京,100081;北京理工大学电子工程系,北京,100081;北京理工大学电子工程系,北京,100081;北京理工大学电子工程系,北京,100081 |
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| 基金项目： | 国防科技预研基金，99J.1.4.8.BQ0108， |
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| 摘 要： | 本文介绍了一种利用0.6μm单硅双铝双阱CMOS工艺实现的4Kbit掩膜ROM专用集成电路设计(ASIC).ROM单元应用串行结构,整个芯片的面积为0.082mm2.在5伏电源下,功率延迟积为0.036PJ/bit,最大工作电流为1.2mA,最大静态漏电流为0.1μA.采用一种新颖的灵敏放大器有效地提高了ROM的访问速度,ROM的访问时间为36ns.
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| 关 键 词： | CMOS工艺 只读存贮器(ROM) 低功耗 译码器 灵敏放大器 |
| 文章编号： | 0372-2112(2002)06-0934-03 |
| 收稿时间： | 2001-06-15 |
A Small Area Low Power Consumption Mask ROM ASIC Design |
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| CUI Wei,HAN Yue-qiu,CHEN He,LI Yun. A Small Area Low Power Consumption Mask ROM ASIC Design[J]. Acta Electronica Sinica, 2002, 30(6): 934-936 |
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| Authors: | CUI Wei HAN Yue-qiu CHEN He LI Yun |
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| Affiliation: | Department of Electronic Engineering,Beijing Institute of Technology,Beijing 100081,China |
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| Abstract: | The ASIC design of a 4K bit mask-programmable CMOS ROM is introduced,and the ROM has a small area of 0.082mm2 with a power-delay product of 0.036PJ/bit.The high packing density and the excellent power-delay product have been achieved by using double well,single polysilicon,double metal 0.6μm CMOS technology and a serial ROM cell structure.The power supply currents in active and quiescent modes are 1.2mA and less than 0.1μA at +5V,respectively.Using a novel and simple sensitive amplifier/driver structure efficiently reduces the memory access time.The memory access time is 36ns. |
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| Keywords: | CMOS technology ROM low consumption decoder sense amplifier |
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