一种用于ASIC芯片测试的多接口CPU模型的VHDL设计

为了对具有不同CPU接口的VHDL语言实现的ASIC芯片进行仿真测试，降低芯片测试的复杂性及成本，本文设计了一个专门用于芯片测试的CPU模型。模型用VHDL语言实现，设计采用了分层次、模块化的设计思想。与现有的VHDL实现的CPU模型相比较，该模型具有结构简单、多接口、高效率、调试使用方便等特点，本文对此CPU模型的设计思想，结构作了介绍和分析。

A VHDL Design of Multi- interface CPU Model for ASIC Test

Test of ASICs with various CPU interfaces often brings considerable complexity and cost.This paper introduces a CPU model specially designed for ASIC test to eliminate such difficulties.The model uses layered structure and is highly modularized,which offers better expandability of both interface and internal function.Comparing with existing models,this one has the advantages of flexible interface,function-expandability,higher efficiency and easier debugging mechanism.This paper introduces the main design thoughts and internal structure of the CPU model.