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An efficient built-in self test method for robust path delay fault testing |
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| Authors: | Ioannis Voyiatzis Antonis Paschalis Dimitrios Nikolos Constantin Halatsis |
| Affiliation: | (1) Institute of Informatics and Telecommunications, NCSR “DEMOKRITOS”, 15310 Aghia Paraskevi, Athens, Greece;(2) Department of Computer Engineering and Informatics, University of Patras, Rio, Patra, Greece;(3) Department of Informatics, University of Athens, TYPA Buildings, 15771, Greece |
| Abstract: | Single Input Change (SIC) testing has been proposed for robust path delay fault testing. In this letter a new Built-In Self Test (BIST) method for SIC vector generation is presented. The proposed method compares favourably to the previously proposed methods for SIC pattern generation with respect to hardware overhead and time required for completion of the test. |
| Keywords: | built-in self test two-pattern test generator single-input change pattern testing robust path delay faults |
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