| 基于FPGA的高效灵活性数字正交下变频器设计 |
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| 引用本文： | 徐伟,王旭东.基于FPGA的高效灵活性数字正交下变频器设计[J].电子技术应用,2012,38(9):5-7. |
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| 作者姓名： | 徐伟 王旭东 |
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| 作者单位： | 南京航空航天大学电子信息工程学院,江苏 南京,210016 |
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| 摘 要： | 数字正交下变频器DDC是数字接收机系统中的核心部件,其作用是将ADC数字化后输出的高速中频信号进行下变频、抽取降速和低通滤波,使之变为适合处理的基带信号。给出了DDC各模块在FPGA中高效实现的方法,并且利用嵌入式逻辑分析仪对系统加载板卡后的实时运行结果进行了测试分析。
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| 关 键 词： | 软件无线电 DDC FPGA |
Design of a high-efficiency and flexible digital down converter based on FPGA |
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| Xu Wei
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Wang Xudong.Design of a high-efficiency and flexible digital down converter based on FPGA[J].Application of Electronic Technique,2012,38(9):5-7. |
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| Authors: | Xu Wei Wang Xudong |
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| Affiliation: | (Eletronic Information Engineering Institute,Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China) |
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| Abstract: | Digital down converter DDC is the core technology in software radio receiver system.After converting down,speeding down and processed by low-pass filter,it can change the IF signal into baseband signal which is suitable for processing signal.This paper introduces a simply and flexible method to realize each module of DDC in FPGA,and get the real-time operation of the system with the SignalTap II logic analyzer. |
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| Keywords: | software radio DDC FPGA |
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