基于锁相环的比率抖动调制数字水印同步算法

针对数字水印中的去同步攻击问题,提出一种基于锁相环的比率抖动调制水印算法。该方法考虑分数平移和幅度缩放两种去同步攻击,水印嵌入器采用比率抖动调制方法,水印检测器采用联合信道参数估计和水印消息解码。其中检测器根据比率抖动调制水印的解码结果,调整去同步攻击参数的估计值,再根据该参数的估计来辅助水印解码,提高解码性能。实验分别测试了有无数据辅助模式和不同插值方式对于该水印系统的影响。实验结果表明,该算法能有效地抵抗分数平移和幅度缩放两种去同步攻击。

PLL-based synchronization of rational dither modulation watermarking

To resist desynchronization attacks, a watermarking scheme using Rational Dither Modulation (RDM) based on Phase-Locked Loop (PLL) was proposed. This scheme took account of two kinds of desynchronization attacks: translation and scaling. Watermark was embedded by RDM and detected by the framework of joint synchronization and decoding. The detector adjusted the estimated attack parameters in PLL according to the results of RDM decoder. Then the new estimated parameters were used to aid watermark decoding, so as to improve the decoding performance. The authors tested the performance of this watermarking system in different data models (DA/DD) and different interpolation algorithms. The simulation results show that this algorithm can resist translation and scaling attacks effectively.