基于IMPULSE C的GF(P)域椭圆加密算法的硬件加速

研究了大素数域上的椭圆曲线加密算法，基于IMPULSE C语言，对该算法进行编程实现；在标准射影坐标系下，对点加和倍加算法进行并行化改进，并且在编程时利用编译器特性做了进一步的并行化。通过对加密算法合理的软硬件分割，将计算量大而且复杂的点乘运算作为硬件部分，通过现场可编程门陈列(FPGA)进行硬件加速；将加密协议的其他部分作为软件部分，在传统CPU上执行，并将硬件部分生成VHDL代码。分别进行加密算法的CoDeveloper的桌面仿真和生成的硬件VHDL代码的ISE综合仿真。最后将该加速设计在Xilinx Virtex-5 xc5vfx70t FPGA开发板上作了实现，基于FPGA的实验结果表明，P-192上点乘运算处理在133MHz时钟下用时2.9 ms，硬件资源分配合理，与现有的手工编写的HDL代码相比，具有并行加速优势。

Hardware acceleration based on IMPULSE C of ECC over GF(P)

Elliptic Curve Cryptography (ECC) based on GF(P) was studied deeply and programmed in IMPULSE C code. Firstly, a parallelization technique was proposed to speed up modular addition and modular doubling in standard projective coordinates, and a further parallelization was given using complier while programming. Secondly, according to the characteristics of IMPULSE C, a rational distribution of ECC algorithm was made. In this design, the complicated point multiplication with a large amount of calculation was regarded as hardware part, which was implemented and accelerated through Field Programmable Gate Array (FPGA). The ECC protocol was regarded as software part and implemented on CPU, and VHDL code was generated for hardware part. The IMPULSE C code was simulated by CoDeveloper and the VHDL code was analyzed and synthesized by Xilinx ISE 10.1.On the basis of the previous work, the design has been prototyped on a Xilinx Virtex-5 xc5vfx70t FPGA board. The experimental result indicate that the proposed method can deal with P-192 point multiplication within 2.9 ms at 133 MHz clock, and shows better throughput compared to the exiting reported realization.