| 基于System Generator的内插位同步法 |
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| 引用本文： | 赵秋明,何克森,陈小飞.基于System Generator的内插位同步法[J].桂林电子科技大学学报,2014(2):96-100. |
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| 作者姓名： | 赵秋明 何克森 陈小飞 |
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| 作者单位： | 桂林电子科技大学 信息与通信学院,广西 桂林541004 |
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| 基金项目： | 国家自然科学基金（11033004） |
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| 摘 要： | 针对数字接收机中如何全数字地实现位同步,设计了一种内插位同步法。利用内插与Gardner算法相结合的原理设计位同步,通过System Generator进行建模仿真,并直接生成代码下载到FPGA实现位同步。利用QPSK信号进行仿真分析,FPGA硬件协同仿真进行验证。实验结果表明,内插位同步法具有很好的位同步效果。
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| 关 键 词： | 内插位同步 System Generator FPGA |
An interpolation bit synchronized method based on System Generator |
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| Zhao Qiuming,He Kesen,Chen Xiaofei.An interpolation bit synchronized method based on System Generator[J].Journal of Guilin Institute of Electronic Technology,2014(2):96-100. |
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| Authors: | Zhao Qiuming He Kesen Chen Xiaofei |
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| Affiliation: | (School of Information and Communication Engineering, Guilin University of Electronic Technology, Guilin 541004, China) |
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| Abstract: | In order to realize the synchronization of the digital receivers,a kind of interpolation bit synchronization method is designed.The bit synchronization is designed by combining interpolation theory with the Gardner algorithm.Through the simulation of System Generator,the generated code is downloaded to the FPGA to achieve the synchronization.The simula-tion analysis uses QPSK signal to verify the FPGA hardware component simulation.The experimental results show that the interpolation bit synchronization method has a good synchronization performance. |
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| Keywords: | System Generator FPGA interpolation synchronization System Generator FPGA |
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