| 一种IEEE802.11n流水线FFT/IFFT的实现 |
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| 引用本文： | 石 钦,林基明,周立国,李彩俊.一种IEEE802.11n流水线FFT/IFFT的实现[J].桂林电子科技大学学报,2014(2):91-95. |
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| 作者姓名： | 石 钦 林基明 周立国 李彩俊 |
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| 作者单位： | [1] 桂林电子科技大学 信息与通信学院,广西 桂林541004 [2] 中国科学院半导体研究所,北京,100083 [3] 灵芯微电子科技 苏州 有限公司,江苏 苏州215021 |
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| 基金项目： | 国家自然科学基金（61261017）：广西自然科学基金（2013GXNSFAA019334） |
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| 摘 要： | 为了解决无线通信系统结构复杂、硬件占用大的问题,设计了一种优化的流水线型FFT/IFFT处理器。该FFT处理器专为IEEE802.11n协议中SISO-OFDM系统设计,根据SISO-OFDM需完成64点、128点快速傅里叶变换(FFT)的特点,FFT处理器选择基2、基4混合算法,单路延迟反馈结构。硬件实现中,采用优化的蝶形运算单元,精简了旋转因子的存储,并设计了动态存取的输出寄存器等,输入输出位宽为10 bit时,在UMC 0.11μm CMOS工艺下将硬件描述优化成逻辑门阵列,面积约为0.3 mm2。与传统的存储器结构FFT相比,大大减少了硬件开销和芯片面积及电路功耗。
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| 关 键 词： | 快速傅里叶变换 单路延迟反馈结构 蝶形运算单元 流水线结构 |
Implementation of an IEEE 802.1 1n pipeline FFT/IFFT |
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| Shi Qin,Lin Jiming,Zhou Liguo,Li Caijun.Implementation of an IEEE 802.1 1n pipeline FFT/IFFT[J].Journal of Guilin Institute of Electronic Technology,2014(2):91-95. |
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| Authors: | Shi Qin Lin Jiming Zhou Liguo Li Caijun |
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| Affiliation: | 1. School of Information and Communication Engineering, Guilin University of Electronic Technology, Guilin 541004, 2. Institute of Semiconductors, Chinese Academy of Science, Beijing 100083, China; 3. SmartChip Microelectronics Science Technology (Suzhou) Co. Ltd. , Suzhou 215021, China) |
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| Abstract: | In order to simplify the complicity of the wireless communication system,a kind of FFT/IFFT processor is de-signed based on the SISO-OFDM system in IEEE 802.11n.Because the SISO-OFDM system needs 64 and 128 points fast Fourier transform,the FFT processor employs radix-4/2 mixed algorithm and single-path delay feedback architecture.The optimized butterfly unit is designed in the hardware.The simplified storage of twiddle factors and an optimized output RAM are also used to minimize the chip area.The 10 bit processor is designed in UMC 110 nm CMOS process,the chip area is a-bout 0.3 mm2 .Compared to the traditional memory based on FFT,the hardware cost and the power consumption are de-creased largely. |
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| Keywords: | fast Fourier transformation single-path delay feedback butterfly operation unit pipeline architecture |
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