A circuit technology for a self-refresh 16 Mb DRAM with less than0.5 μA/MB data-retention current |
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Authors: | Yamauchi H Iwata T Uno A Fukumoto M Fujita T |
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Affiliation: | Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka; |
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Abstract: | A 16M self-refresh DRAM achieving less than 0.5 μA per megabyte data retention current has been developed. Several techniques to achieve low retention current, including a relaxed junction biasing (RTB) scheme, a plate-floating leakage-monitoring (PFM) system, and a VBB pull-down word-line driver (PDWD) are described. An extension of data-retention time by three-fold and the refresh timer period by 30-fold over previously reported self-refresh DRAMs has been achieved. This results in a reduction of the ac refresh-current to less than 0.4 μA per megabyte. Furthermore, the addition of a gate-received VBB detector (GRD) reduces dc retention current to less than 0.1 μA per megabyte. This allows a 20-megabyte RAM disk to retain data for 2.5 years when powered by a single button-shaped 190-mAh lithium battery |
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