| 用于1.25GHz Serdes的低时钟抖动的环振的设计 |
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| 引用本文： | 肖磊,刘玮,杨莲兴.用于1.25GHz Serdes的低时钟抖动的环振的设计[J].半导体学报,2008,29(3). |
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| 作者姓名： | 肖磊 刘玮 杨莲兴 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室,上海,201203 |
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| 摘 要： | 设计了一种新的用于电压控制振荡器的延迟单元,并与源级耦合差分延时单元的时钟抖动进行了比较.提出了基于低时钟抖动的锁相环环路参数的优化技术.在0.35μm CMOS工艺下进行1.25GHz Serdes流片,测试表明数据率为1.25GHz的高速串联输出的随机抖动均方根为2.3ps(归一化为0.0015UI),随机抖动标准偏差为0.0035UI.在1111100000的数据输出时相位噪声为-120dBc/Hz@100kHz.
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| 关 键 词： | 低时钟抖动 环振 电源噪声抑制 串并.并串转换 |
A Low Jitter Design of Ring Oscillators in 1.25GHz Serdes |
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| Xiao Lei,Liu Wei,Yang Lianxing.A Low Jitter Design of Ring Oscillators in 1.25GHz Serdes[J].Chinese Journal of Semiconductors,2008,29(3). |
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| Authors: | Xiao Lei Liu Wei Yang Lianxing |
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| Abstract: | A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison be- tween the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ (random jitter) RMS of 1.25GHz data rate series output is 2. 3ps (0. 0015UI) and RJ (1 sigma) is 0. 0035UI. A phase noise measurement shows-120dBc/Hz@100kHz at 1111100000 clock-pattern data out. |
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| Keywords: | Serdes voltage controlled ring oscillator low jitter |
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