CMOS射频集成电路ESD保护的挑战

随着集成电路(IC)T艺进入深亚微米水平,以及射频(Radi0.Frequency,RF)IC工作频率向数千兆赫兹频段迈进,片上防静电泄放(ESD)保护设计越来越成为RF IC设计的挑战.产生这一挑战的关键原因在于ESD保护电路和被保护的RF IC核电路之间存在着不可避免的复杂交互影响效应.本文讨论了RF ESD保护的研究和设计领域的最新动态,总结了所出现的新挑战、新的设计方法和最新的RF ESD保护解决方案.

Emerging Challenges in ESD Protection for RF ICs in CMOS

On-chip electrostatic discharge (ESD) protection design has become an emerging challenge for radio-frequency(RF) integrated circuits (IC) design as IC technologies migrate into the very-deep-sub-micron (VDSM) regime and RFICs move into multi-GHz operations. The key problem originates from the complex interaction between the ESD protec-tion circuitry and the core RF IC circuit under protection. This paper discusses the recent development in RF ESD protec-tion research and design,outlining emerging challenges,new design methods,and novel RF ESD protection solutions.